`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/08/20 15:00:26
// Design Name: 
// Module Name: top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module top(
   // clk_from_7044
    input clk_27dr_p,   
    input clk_27dr_n, 
    // spi
    output  o_fpga_spi0_mosi          ,
    output  o_fpga_spi0_sclk          ,
    output  o_hmc7044_spi_slen        ,
    inout   io_hmc7044_spi_sdata      ,
    output  o_hmc7044_spi_sclk        ,
    output  o_lmx2594_a_spi1_ss       ,
    input   i_lmx2594_a_spi1_miso     ,
    output  o_lmx2594_a_spi1_mosi     ,
    output  o_lmx2594_a_spi1_sclk     ,                           
    output  o_lmx2594_b_spi1_ss       ,
    input   i_lmx2594_b_spi1_miso     ,
    output  o_lmx2594_b_spi1_mosi     ,
    output  o_lmx2594_b_spi1_sclk     ,                           
    output  o_lmx2594_c_spi1_ss       ,
    input   i_lmx2594_c_spi1_miso     ,
    output  o_lmx2594_c_spi1_mosi     ,
    output  o_lmx2594_c_spi1_sclk     ,

    // gpio
    inout   o_i2c_reset_b           ,
    inout   i_int_adt7516           ,
    inout   i_hmc7044_gpio3         ,
    inout   i_hmc7044_gpio2         ,
    inout   i_hmc7044_gpio1         ,
    inout   o_hmc7044_rst           ,
    inout   o_hmc7044_sync          ,
    inout   i_id1                   ,
    inout   i_id2                   ,
    inout   i_id3                   ,
    inout   i_id4                   ,
    inout   i_zynq2vu_done          ,
    inout   i_vu_init_b             ,
    inout   o_vu_prog_b             ,
    
    
    
    // rf_dc
    input adc0_clk_clk_n,
    input adc0_clk_clk_p,
    input adc1_clk_clk_n,
    input adc1_clk_clk_p,
    input adc2_clk_clk_n,
    input adc2_clk_clk_p,
    input adc3_clk_clk_n,
    input adc3_clk_clk_p,
    input dac0_clk_clk_n,
    input dac0_clk_clk_p,
    input dac1_clk_clk_n,
    input dac1_clk_clk_p,
   
    input sysref_in_diff_n, 
    input sysref_in_diff_p,
    
    input sysref_fpga_p,   
    input sysref_fpga_n,
    
    input fpga_fclk_156p25_p,
    input fpga_fclk_156p25_n,
    
    input vin0_01_v_n,
    input vin0_01_v_p,
    input vin0_23_v_n,
    input vin0_23_v_p,
    input vin1_01_v_n,
    input vin1_01_v_p,
    input vin1_23_v_n,
    input vin1_23_v_p,
    input vin2_01_v_n,
    input vin2_01_v_p,
    input vin2_23_v_n,
    input vin2_23_v_p,
    input vin3_01_v_n,
    input vin3_01_v_p,
    input vin3_23_v_n,
    input vin3_23_v_p,
    output vout00_v_n,
    output vout00_v_p,
    output vout01_v_n,
    output vout01_v_p,
    output vout02_v_n,
    output vout02_v_p,
    output vout03_v_n,
    output vout03_v_p,
    output vout10_v_n,
    output vout10_v_p,
    output vout11_v_n,
    output vout11_v_p,
    output vout12_v_n,
    output vout12_v_p,
    output vout13_v_n,
    output vout13_v_p,
    // led status
    output [4 : 0] gpio_led
    
    );
 `include "xczu27dr_def.v"
 wire                       clk_axi                         ;
 wire                       pl_resetn0                      ;

 wire  [31:0]               s_axi_apb_awaddr                ;
 wire                       s_axi_apb_awvalid               ;
 wire                       s_axi_apb_awready               ;
 wire  [31:0]               s_axi_apb_wdata                 ;
 wire                       s_axi_apb_wvalid                ;
 wire                       s_axi_apb_wready                ;
 wire  [1:0]                s_axi_apb_bresp                 ;
 wire                       s_axi_apb_bvalid                ;
 wire                       s_axi_apb_bready                ;
 wire  [31:0]               s_axi_apb_araddr                ;
 wire                       s_axi_apb_arvalid               ;
 wire                       s_axi_apb_arready               ;
 wire  [31:0]               s_axi_apb_rdata                 ;
 wire  [1:0]                s_axi_apb_rresp                 ;
 wire                       s_axi_apb_rvalid                ;
 wire                       s_axi_apb_rready                ;
//  wire [11:0]                s_axi_apb_arid                  ;
//  wire [11:0]                s_axi_apb_awid                  ; 




 wire emio_rst              ;
 
 // reset
 wire ps2pl_gpio_rst;
 wire pl_rst;        // reset == 1 ; release == 0
 // clock
 wire fpga_fclk_156p25;          //
 wire fpga_adc_clk_491p52;       //
 wire fpga_dac_clk_245p76;       //
 // adc pin
 wire [127 : 0] m00_axis_0_tdata;
 wire m00_axis_0_tready;
 wire m00_axis_0_tvalid;
 wire [127 : 0] m02_axis_0_tdata;
 wire m02_axis_0_tready;
 wire m02_axis_0_tvalid;
 wire m0_axis_aclk_0;
 wire m0_axis_aresetn_0;

 wire [127 : 0] m10_axis_0_tdata;
 wire m10_axis_0_tready;
 wire m10_axis_0_tvalid;
 wire [127 : 0]m12_axis_0_tdata;
 wire m12_axis_0_tready;
 wire m12_axis_0_tvalid;
 wire m1_axis_aclk_0;
 wire m1_axis_aresetn_0;

 wire [127 : 0] m20_axis_0_tdata;
 wire m20_axis_0_tready;
 wire m20_axis_0_tvalid;
 wire [127 : 0] m22_axis_0_tdata;
 wire m22_axis_0_tready;
 wire m22_axis_0_tvalid;
 wire m2_axis_aclk_0;
 wire m2_axis_aresetn_0;

 wire [127 : 0] m30_axis_0_tdata;
 wire m30_axis_0_tready;
 wire m30_axis_0_tvalid;
 wire [127 : 0] m32_axis_0_tdata;
 wire m32_axis_0_tready;
 wire m32_axis_0_tvalid;
 wire m3_axis_aclk_0;
 wire m3_axis_aresetn_0;
 
 // dac pin
 wire s0_axis_aresetn_0;
 wire s1_axis_aresetn_0;
 wire dac_data_ready_0;
 wire dac_data_ready_1;
 wire dac_data_ready_2;
 wire dac_data_ready_3;
 wire dac_data_ready_4;
 wire dac_data_ready_5;
 wire dac_data_ready_6;
 wire dac_data_ready_7;

 wire dac_data_valid;
 wire [255 : 0] dac_data;
 wire dac_data_ready;
 wire user_sysref_adc_0;
 wire user_sysref_dac_0;
    
 assign ps2pl_gpio_rst = ~emio_rst; // gpio429
 
//  assign gpio_led[4] = m00_axis_0_tvalid;      // led3   1 --> on ; 0 --> off
//  assign gpio_led[3] = dac_data_valid;         // led2
//  assign gpio_led[2] = pl_rst;                 // led1
//  assign gpio_led[1] = m0_axis_aresetn_0;      // led4
//  assign gpio_led[0] = dac_data_ready;         // led5

 
 // ADC_ready and DAC_ready input
 assign dac_data_ready = dac_data_ready_0;
 assign m00_axis_0_tready = 1;
 assign m02_axis_0_tready = 1;
 assign m10_axis_0_tready = 1;
 assign m12_axis_0_tready = 1;
 assign m20_axis_0_tready = 1;
 assign m22_axis_0_tready = 1;
 assign m30_axis_0_tready = 1;
 assign m32_axis_0_tready = 1;

 // axi reset
 assign m0_axis_aresetn_0 = ~pl_rst;
 assign m1_axis_aresetn_0 = ~pl_rst;
 assign m2_axis_aresetn_0 = ~pl_rst;
 assign m3_axis_aresetn_0 = ~pl_rst;
 assign s0_axis_aresetn_0 = ~pl_rst;
 assign s1_axis_aresetn_0 = ~pl_rst;

   wire clk_27dr          ;
   wire clk_491p52        ;
   wire clk_245p76        ;
   wire  reg_reset        ;
   wire  clk_inst_locked  ;
   wire  ctrl_led         ;

   test_7044clk test_7044clk_inst (
      .clk_27dr_p       ( clk_27dr_p )       ,   
      .clk_27dr_n       ( clk_27dr_n )       ,
      .clk_27dr         ( clk_27dr   )       ,
      .clk_491p52       ( clk_491p52  )      ,     
      .clk_245p76       ( clk_245p76  )      ,
      .reg_reset        ( reg_reset   )      ,
      .clk_inst_locked  ( clk_inst_locked )  
   );
   reg clk_locked   = 1'b0    ;
   reg clk_led      = 1'b0    ;
   reg clk15625_led = 1'b0    ;
   reg clk49125_led = 1'b0    ;
   reg [31 : 0 ] clk_cnt_d = 32'd0;
   localparam CNT_MAX   = 32'd122880000; // 122.88MHz / 491.52MHz
   assign gpio_led[0] = clk49125_led;
   assign gpio_led[1] = clk15625_led;
   assign gpio_led[2] = ctrl_led;
   assign gpio_led[3] = clk_inst_locked;
   assign gpio_led[4] = clk_led;
   always @(posedge clk_27dr ) begin
      if (clk_cnt_d == CNT_MAX)
         clk_cnt_d <= 0;
      else
         clk_cnt_d <= clk_cnt_d + 1'b1;
   end
   always @(posedge clk_27dr ) begin
      if( clk_cnt_d == CNT_MAX )
         clk_led <= ~clk_led;
      else
         clk_led <= clk_led;
   end
   always @(posedge clk_491p52 ) begin
      clk_locked <= clk_inst_locked;
   end
   localparam CNT_MAX_15625   = 32'd156250000; // 156.25M
   reg [31 : 0 ] clk15625_cnt_d = 32'd0;
   always @(posedge fpga_fclk_156p25 ) begin
      if (clk15625_cnt_d == CNT_MAX_15625)
         clk15625_cnt_d <= 0;
      else
         clk15625_cnt_d <= clk15625_cnt_d + 1'b1;     
   end
   always @(posedge fpga_fclk_156p25 ) begin
      if( clk15625_cnt_d == CNT_MAX_15625 )
         clk15625_led <= ~clk15625_led;
      else
         clk15625_led <= clk15625_led;
   end
   localparam CNT_MAX_49125   = 32'd491250000; // 491.25M
   reg [31 : 0 ] clk49125_cnt_d = 32'd0;
   always @(posedge clk_491p52 ) begin
      if (clk49125_cnt_d == CNT_MAX_49125)
         clk49125_cnt_d <= 0;
      else
         clk49125_cnt_d <= clk49125_cnt_d + 1'b1;     
   end
   always @(posedge clk_491p52 ) begin
      if( clk49125_cnt_d == CNT_MAX_49125 )
         clk49125_led <= ~clk49125_led;
      else
         clk49125_led <= clk49125_led;
   end
 clk_gen clk_gen_0(
    .ps2pl_gpio_rst(ps2pl_gpio_rst),
    .fpga_fclk_156p25_p(fpga_fclk_156p25_p),
    .fpga_fclk_156p25_n(fpga_fclk_156p25_n),

    .fpga_fclk_156p25(fpga_fclk_156p25),
    .fpga_adc_clk_491p52(fpga_adc_clk_491p52),     
    .fpga_dac_clk_245p76(fpga_dac_clk_245p76),    
    .pl_rst(pl_rst)
 );
 
 rom_dac_in rom_dac_0(
    .fpga_dac_clk_245p76(fpga_dac_clk_245p76),
    .pl_rst(pl_rst),
    .dac_data_ready(dac_data_ready),
    
    .dac_data(dac_data),
    .dac_data_valid(dac_data_valid)
 );

 mts_process mts_process_0(
    .sysref_fpga_p(sysref_fpga_p),
    .sysref_fpga_n(sysref_fpga_n),
    .fpga_adc_clk_491p52(fpga_adc_clk_491p52),     //ADC-245.76M
    .fpga_dac_clk_245p76(fpga_dac_clk_245p76),    //DAC-245.76M
    .pl_rst(pl_rst),
    
    .user_sysref_adc(user_sysref_adc_0),  //less than 10M
    .user_sysref_dac(user_sysref_dac_0)   //less than 10M
 );


 axi2apb_bridge u_axi2apb_bridge(
   .s_axi_aclk        (  clk_axi                    ), 
   .s_axi_aresetn     (  pl_resetn0                 ), 
   .s_axi_awaddr      (  s_axi_apb_awaddr           ), 
   .s_axi_awvalid     (  s_axi_apb_awvalid          ), 
   .s_axi_awready     (  s_axi_apb_awready          ), 
   .s_axi_wdata       (  s_axi_apb_wdata            ), 
   .s_axi_wvalid      (  s_axi_apb_wvalid           ), 
   .s_axi_wready      (  s_axi_apb_wready           ), 
   .s_axi_bresp       (  s_axi_apb_bresp            ), 
   .s_axi_bvalid      (  s_axi_apb_bvalid           ), 
   .s_axi_bready      (  s_axi_apb_bready           ), 
   .s_axi_araddr      (  s_axi_apb_araddr           ), 
   .s_axi_arvalid     (  s_axi_apb_arvalid          ), 
   .s_axi_arready     (  s_axi_apb_arready          ), 
   .s_axi_rdata       (  s_axi_apb_rdata            ), 
   .s_axi_rresp       (  s_axi_apb_rresp            ), 
   .s_axi_rvalid      (  s_axi_apb_rvalid           ), 
   .s_axi_rready      (  s_axi_apb_rready           ),
   .soft_clk_27dr_reset   (reg_reset) ,
   .ctrl_led              (ctrl_led)
   // reserved for other module
   // .paddr             (  paddr                      ), 
   // .psel_phy          (  psel_phy                   ), 
   // .penable           (  penable                    ), 
   // .pwrite            (  pwrite                     ), 
   // .pwdata            (  pwdata                     ), 
   // .prdata_phy        (  prdata_phy                 )
 );

 ps_top u_ps_top(
    // spi
    .o_fpga_spi0_mosi          ( o_fpga_spi0_mosi )          ,
    .o_fpga_spi0_sclk          ( o_fpga_spi0_sclk )          ,
    .o_hmc7044_spi_slen        ( o_hmc7044_spi_slen )        ,
    .io_hmc7044_spi_sdata      ( io_hmc7044_spi_sdata )      ,
    .o_hmc7044_spi_sclk        ( o_hmc7044_spi_sclk )        ,
    .o_lmx2594_a_spi1_ss       ( o_lmx2594_a_spi1_ss )       ,
    .i_lmx2594_a_spi1_miso     ( i_lmx2594_a_spi1_miso )     ,
    .o_lmx2594_a_spi1_mosi     ( o_lmx2594_a_spi1_mosi )     ,
    .o_lmx2594_a_spi1_sclk     ( o_lmx2594_a_spi1_sclk )     ,                        
    .o_lmx2594_b_spi1_ss       ( o_lmx2594_b_spi1_ss )       ,
    .i_lmx2594_b_spi1_miso     ( i_lmx2594_b_spi1_miso )     ,
    .o_lmx2594_b_spi1_mosi     ( o_lmx2594_b_spi1_mosi )     ,
    .o_lmx2594_b_spi1_sclk     ( o_lmx2594_b_spi1_sclk )     ,                      
    .o_lmx2594_c_spi1_ss       ( o_lmx2594_c_spi1_ss )       ,
    .i_lmx2594_c_spi1_miso     ( i_lmx2594_c_spi1_miso )     ,
    .o_lmx2594_c_spi1_mosi     ( o_lmx2594_c_spi1_mosi )     ,
    .o_lmx2594_c_spi1_sclk     ( o_lmx2594_c_spi1_sclk )     , 
    
    // gpio emio define
    .o_rfdc_rst                ( emio_rst )                  ,
    .o_i2c_reset_b             ( o_i2c_reset_b )             ,
    .i_int_adt7516             ( i_int_adt7516 )             ,
    .i_hmc7044_gpio3           ( i_hmc7044_gpio3 )           ,
    .i_hmc7044_gpio2           ( i_hmc7044_gpio2 )           ,
    .i_hmc7044_gpio1           ( i_hmc7044_gpio1 )           ,
    .o_hmc7044_rst             ( o_hmc7044_rst )             ,
    .o_hmc7044_sync            ( o_hmc7044_sync )            ,
    .i_id1                     ( i_id1 )                     ,
    .i_id2                     ( i_id2 )                     ,
    .i_id3                     ( i_id3 )                     ,
    .i_id4                     ( i_id4 )                     ,
    .i_zynq2vu_done            ( i_zynq2vu_done )            ,
    .i_vu_init_b               ( i_vu_init_b )               ,
    .o_vu_prog_b               ( o_vu_prog_b )               ,
  
    
    // axi-lite for axi2apb bridge
    .o_axi_apb_araddr               (s_axi_apb_araddr)       ,
    .o_axi_apb_arprot               ( )                      ,
    .i_axi_apb_arready              (s_axi_apb_arready)      ,
    .o_axi_apb_arvalid              (s_axi_apb_arvalid)      ,
    .o_axi_apb_awaddr               (s_axi_apb_awaddr)       ,
    .o_axi_apb_awprot               ( )                      ,
    .i_axi_apb_awready              (s_axi_apb_awready)      ,
    .o_axi_apb_awvalid              (s_axi_apb_awvalid)      ,
    .o_axi_apb_bready               (s_axi_apb_bready)       ,
    .i_axi_apb_bresp                (s_axi_apb_bresp)        ,
    .i_axi_apb_bvalid               (s_axi_apb_bvalid)       ,
    .i_axi_apb_rdata                (s_axi_apb_rdata)        ,
    .o_axi_apb_rready               (s_axi_apb_rready)       ,
    .i_axi_apb_rresp                (s_axi_apb_rresp)        ,
    .i_axi_apb_rvalid               (s_axi_apb_rvalid)       ,
    .o_axi_apb_wdata                (s_axi_apb_wdata)        ,
    .i_axi_apb_wready               (s_axi_apb_wready)       ,
    .o_axi_apb_wstrb                ( )                      ,
    .o_axi_apb_wvalid               (s_axi_apb_wvalid)       ,
    .o_axi_lite_clk                 ( clk_axi )              ,
    .o_pl_resetn0                   ( pl_resetn0 )           ,
    
    // rf_dc
    .adc0_clk_clk_n                 ( adc0_clk_clk_n )       ,
    .adc0_clk_clk_p                 ( adc0_clk_clk_p )       ,
    .adc1_clk_clk_n                 ( adc1_clk_clk_n )       ,
    .adc1_clk_clk_p                 ( adc1_clk_clk_p )       ,
    .adc2_clk_clk_n                 ( adc2_clk_clk_n )       ,
    .adc2_clk_clk_p                 ( adc2_clk_clk_p )       ,
    .adc3_clk_clk_n                 ( adc3_clk_clk_n )       ,
    .adc3_clk_clk_p                 ( adc3_clk_clk_p )       ,
    .dac0_clk_clk_n                 ( dac0_clk_clk_n )       ,
    .dac0_clk_clk_p                 ( dac0_clk_clk_p )       ,
    .dac1_clk_clk_n                 ( dac1_clk_clk_n )       ,
    .dac1_clk_clk_p                 ( dac1_clk_clk_p )       ,
   
    .sysref_in_diff_n               ( sysref_in_diff_n )     , 
    .sysref_in_diff_p               ( sysref_in_diff_p )     ,
    
    .user_sysref_adc_0              ( user_sysref_adc_0 )    ,
    .user_sysref_dac_0              ( user_sysref_dac_0 )    ,
    
    .vin0_01_v_n                    ( vin0_01_v_n )          ,
    .vin0_01_v_p                    ( vin0_01_v_p )          ,
    .vin0_23_v_n                    ( vin0_23_v_n )          ,
    .vin0_23_v_p                    ( vin0_23_v_p )          ,
    .vin1_01_v_n                    ( vin1_01_v_n )          ,
    .vin1_01_v_p                    ( vin1_01_v_p )          ,
    .vin1_23_v_n                    ( vin1_23_v_n )          ,
    .vin1_23_v_p                    ( vin1_23_v_p )          ,
    .vin2_01_v_n                    ( vin2_01_v_n )          ,
    .vin2_01_v_p                    ( vin2_01_v_p )          ,
    .vin2_23_v_n                    ( vin2_23_v_n )          ,
    .vin2_23_v_p                    ( vin2_23_v_p )          ,
    .vin3_01_v_n                    ( vin3_01_v_n )          ,
    .vin3_01_v_p                    ( vin3_01_v_p )          ,
    .vin3_23_v_n                    ( vin3_23_v_n )          ,
    .vin3_23_v_p                    ( vin3_23_v_p )          ,
    .vout00_v_n                     ( vout00_v_n )           ,
    .vout00_v_p                     ( vout00_v_p )           ,
    .vout01_v_n                     ( vout01_v_n )           ,
    .vout01_v_p                     ( vout01_v_p )           ,
    .vout02_v_n                     ( vout02_v_n )           ,
    .vout02_v_p                     ( vout02_v_p )           ,
    .vout03_v_n                     ( vout03_v_n )           ,
    .vout03_v_p                     ( vout03_v_p )           ,
    .vout10_v_n                     ( vout10_v_n )           ,
    .vout10_v_p                     ( vout10_v_p )           ,
    .vout11_v_n                     ( vout11_v_n )           ,
    .vout11_v_p                     ( vout11_v_p )           ,
    .vout12_v_n                     ( vout12_v_n )           ,
    .vout12_v_p                     ( vout12_v_p )           ,
    .vout13_v_n                     ( vout13_v_n )           ,
    .vout13_v_p                     ( vout13_v_p )           ,
     
    .m00_axis_0_tdata                ( m00_axis_0_tdata )    ,
    .m00_axis_0_tready               ( m00_axis_0_tready )   ,
    .m00_axis_0_tvalid               ( m00_axis_0_tvalid )   ,
    .m02_axis_0_tdata                ( m02_axis_0_tdata )    ,
    .m02_axis_0_tready               ( m02_axis_0_tready )   ,
    .m02_axis_0_tvalid               ( m02_axis_0_tvalid )   ,
    .m0_axis_aclk_0                  ( fpga_adc_clk_491p52 ) , // adc 491.25m
    .m0_axis_aresetn_0               ( m0_axis_aresetn_0 )   ,
    .m10_axis_0_tdata                ( m10_axis_0_tdata )    ,
    .m10_axis_0_tready               ( m10_axis_0_tready )   ,
    .m10_axis_0_tvalid               ( m10_axis_0_tvalid )   ,
    .m12_axis_0_tdata                ( m12_axis_0_tdata )    ,
    .m12_axis_0_tready               ( m12_axis_0_tready )   ,
    .m12_axis_0_tvalid               ( m12_axis_0_tvalid )   ,
    .m1_axis_aclk_0                  ( fpga_adc_clk_491p52 ) ,
    .m1_axis_aresetn_0               ( m1_axis_aresetn_0 )   ,
    .m20_axis_0_tdata                ( m20_axis_0_tdata )    ,
    .m20_axis_0_tready               ( m20_axis_0_tready )   ,
    .m20_axis_0_tvalid               ( m20_axis_0_tvalid )   ,
    .m22_axis_0_tdata                ( m22_axis_0_tdata)     ,
    .m22_axis_0_tready               ( m22_axis_0_tready)    ,
    .m22_axis_0_tvalid               ( m22_axis_0_tvalid)    ,
    .m2_axis_aclk_0                  ( fpga_adc_clk_491p52)  ,
    .m2_axis_aresetn_0               ( m2_axis_aresetn_0)    ,
    .m30_axis_0_tdata                ( m30_axis_0_tdata)     ,
    .m30_axis_0_tready               ( m30_axis_0_tready)    ,
    .m30_axis_0_tvalid               ( m30_axis_0_tvalid)    ,
    .m32_axis_0_tdata                ( m32_axis_0_tdata)     ,
    .m32_axis_0_tready               ( m32_axis_0_tready)    ,
    .m32_axis_0_tvalid               ( m32_axis_0_tvalid)    ,
    .m3_axis_aclk_0                  ( fpga_adc_clk_491p52)  ,
    .m3_axis_aresetn_0               ( m3_axis_aresetn_0)    ,

    .s00_axis_0_tdata                ( dac_data)             ,
    .s00_axis_0_tready               ( dac_data_ready_0)     ,
    .s00_axis_0_tvalid               ( dac_data_valid)       ,
    .s01_axis_0_tdata                ( dac_data)             ,
    .s01_axis_0_tready               ( dac_data_ready_1)     ,
    .s01_axis_0_tvalid               ( dac_data_valid)       ,
    .s02_axis_0_tdata                ( dac_data)             ,
    .s02_axis_0_tready               ( dac_data_ready_2)     ,
    .s02_axis_0_tvalid               ( dac_data_valid)       ,
    .s03_axis_0_tdata                ( dac_data)             ,
    .s03_axis_0_tready               ( dac_data_ready_3)     ,
    .s03_axis_0_tvalid               ( dac_data_valid)       ,
    .s0_axis_aclk_0                  ( fpga_dac_clk_245p76)  , // dac 245.76
    .s0_axis_aresetn_0               ( s0_axis_aresetn_0)    ,

    .s10_axis_0_tdata                ( dac_data)             ,
    .s10_axis_0_tready               ( dac_data_ready_4)     ,
    .s10_axis_0_tvalid               ( dac_data_valid)       ,
    .s11_axis_0_tdata                ( dac_data)             ,
    .s11_axis_0_tready               ( dac_data_ready_5)     ,
    .s11_axis_0_tvalid               ( dac_data_valid)       ,
    .s12_axis_0_tdata                ( dac_data)             ,
    .s12_axis_0_tready               ( dac_data_ready_6)     ,
    .s12_axis_0_tvalid               ( dac_data_valid)       ,
    .s13_axis_0_tdata                ( dac_data)             ,
    .s13_axis_0_tready               ( dac_data_ready_7)     ,
    .s13_axis_0_tvalid               ( dac_data_valid)       ,
    .s1_axis_aclk_0                  ( fpga_dac_clk_245p76)  ,
    .s1_axis_aresetn_0               ( s1_axis_aresetn_0 )
    );

   // debug
   (* MARK_DEBUG="true" *) reg [127 : 0]      m00_axis_0_tdata_d   ;
   (* MARK_DEBUG="true" *) reg [127 : 0]      m02_axis_0_tdata_d   ;
   (* MARK_DEBUG="true" *) reg [127 : 0]      m10_axis_0_tdata_d   ;
   (* MARK_DEBUG="true" *) reg [127 : 0]      m12_axis_0_tdata_d   ;
   (* MARK_DEBUG="true" *) reg [127 : 0]      m20_axis_0_tdata_d   ;
   (* MARK_DEBUG="true" *) reg [127 : 0]      m22_axis_0_tdata_d   ;
   (* MARK_DEBUG="true" *) reg [127 : 0]      m30_axis_0_tdata_d   ;
   (* MARK_DEBUG="true" *) reg [127 : 0]      m32_axis_0_tdata_d   ;
   
   always @(posedge fpga_adc_clk_491p52 )
   begin
         m00_axis_0_tdata_d  <= m00_axis_0_tdata;
         m02_axis_0_tdata_d  <= m02_axis_0_tdata;
         m10_axis_0_tdata_d  <= m10_axis_0_tdata;
         m12_axis_0_tdata_d  <= m12_axis_0_tdata;
         m20_axis_0_tdata_d  <= m20_axis_0_tdata;
         m22_axis_0_tdata_d  <= m22_axis_0_tdata;
         m30_axis_0_tdata_d  <= m30_axis_0_tdata;
         m32_axis_0_tdata_d  <= m32_axis_0_tdata;
   end


   (* MARK_DEBUG="true" *) reg clk_locked_d ;
   always @(posedge clk_491p52 ) begin
      clk_locked_d <= clk_locked;
   end

    
endmodule



